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Chapter 8: Using Black Boxes for HDL Subsystems
8–11
Subsystem Builder Design Example
Simulating the Subsystem Builder Model
To run the Simulink simulation, follow these steps:
1. Click Start on the Simulation menu in the filter8tap.mdl window to begin the
simulation.
2. Double-click the Scope block to view the simulation results. Click Autoscale to
resize the scope.
3. Click the Zoom X-axis icon and use the cursor to zoom in on the first 22 x-axis time
units.
Figure 8–9 shows the simulation results.
Figure 8–9. Simulink Simulation Results of 8-Tap FIR Filter, Scope Window
1
Because the input is a pulse, the simulation results show the impulse response of the
8-tap FIR filter, which translates to the eight coefficient values. You can change the
input stimulus to verify the step and random response of the filter.
Adding VHDL Dependencies to the Quartus II Project and ModelSim
The VHDL file is dependent on two other VHDL files. The Quartus II software or
ModelSim do not examine these two files, and compilation either fails or gives
unexpected results. To resolve this issue, follow these steps:
1. Double-click on the Signal Compiler block and click Compile . Ignore the result
for now. This action creates a DSPBuilder_filter8tap_import directory in the
directory containing your design.
1
Alternatively, you can create the directory DSPBuilder_filter8tap_import
directly.
2. Copy the extra_add.tcl and extra_add_msim.tcl files from the original design
directory to the DSPBuilder_filter8tap_import directory.
The extra_add.tcl file adds final_add.vhd and four_mult_add.vhd to the Quartus II
project, while extra_add_msim.tcl compiles them in ModelSim when your design is
run using the TestBench block. The Quartus II software executes any files ending with
_add.tcl when it creates the project. ModelSim executes files ending with
_add_msim.tcl when it compiles your design testbench.
November 2013
Altera Corporation
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
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